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ATmega16HVB データシート(PDF) 34 Page - ATMEL Corporation |
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ATmega16HVB データシート(HTML) 34 Page - ATMEL Corporation |
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34 / 273 page  34 8042A–AVR–07/09 ATmega16HVB/32HVB • Bit 4 - OSISEL0: Oscillator Sampling Interface Select 0 • Bit 1 – OSIST: Oscillator Sampling Interface Status This bit continuously displays the phase of the prescaled clock. This bit can be polled by the CPU to determine the rising and falling edges of the prescaled clock. • Bit 0 – OSIEN: Oscillator Sampling Interface Enable Setting this bit enables the Oscillator Sampling Interface. When this bit is cleared, the Oscillator Sampling Interface is disabled. Notes: 1. The prescaler is reset each time the OSICSR register is written, and hence each time a new oscillator source is selected. 2. Enabling the OSI module and selecting Slow RC Oscillator as input source is the only way to enable the Slow RC Oscillator. The Slow RC Oscillator will not run in any other modes. Table 9-6. OSISEL Bit Description OSISEL0 Oscillator source 0 ULP Oscillator 1 Slow RC Oscillator |
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