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MAXQ3180-RAN+ データシート(PDF) 34 Page - Maxim Integrated Products |
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MAXQ3180-RAN+ データシート(HTML) 34 Page - Maxim Integrated Products |
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34 / 101 page ![]() Low-Power, Multifunction, Polyphase AFE 34 ______________________________________________________________________________________ Interrupt Mask Register (IRQ_MASK) (0x006) BIT NAME FUNCTION 15 EDSPOR When set, this flag causes the IRQ pin to become active. 14 EDSPRDY When set, this flag causes the IRQ pin to become active. 13 EDCHR When set, this flag causes the IRQ pin to become active when the direction of reactive energy flow has been observed to have changed (that is, from capacitive to inductive or from inductive to capacitive). 12 EDCHA When set, this flag causes the IRQ pin to become active when the direction of real energy flow has been observed to have changed (that is, from toward the load to away from the load, or from away from the load to toward the load). 11 ENOZX When set, this flag causes the IRQ pin to become active when the MAXQ3180 has failed to detect zero crossings on one or more voltage channels for at least one DSP cycle. 10 EUV When set, this flag causes the IRQ pin to become active when the absolute instantaneous voltage level in one or more voltage channels failed to exceed the trip level set in the UVLVL (Undervoltage Level) register for one DSP cycle. 9 EOV When set, this flag causes the IRQ pin to become active when the absolute instantaneous voltage level in one or more voltage channels has exceeded the trip level set in the OVLVL (Overvoltage Level) register. 8 EOC When set, this flag causes the IRQ pin to become active when absolute instantaneous current in one or more current channels has exceeded the trip level set in the OCLVL (Overcurrent Level) register. 7:3 — Reserved. 2 EEOVF When set, this flag causes the IRQ pin to become active when one or more energy accumulators have an overflow condition from their MSB. 1 ECHSCH When set, this flag enables the IRQ pin to become active when a CHKSUM change is detected. 0 EPWRF When set, this flag causes the IRQ pin to become active when a power-supply failure is imminent and the supervisory processor should begin taking steps to save its state and prepare for a loss of power. Bit: 15 14 13 12 11 10 9 8 Name: EDSPOR EDSPRDY EDCHR EDCHA ENOZX EUV EOV EOC Reset: 0 0 0 0 0 0 0 0 Bit: 7 6 5 4 3 2 1 0 Name: — — — — — EEOVF ECHSCH EPWRF Reset: 0 0 0 0 0 0 0 0 |
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