8

X24C16

Sequential Read

Sequential reads can be initiated as either a current

address read or random access read. The first word is

transmitted as with the other read modes, however, the

master now responds with an acknowledge, indicating it

requires additional data. The X24C16 continues to out-

put data for each acknowledge received. The read

operation is terminated by the master; by not responding

with an acknowledge and by issuing a stop condition.

The data output is sequential, with the data from address

n followed by the data from n + 1. The address counter

for read operations increments all address bits, allowing

the entire memory contents to be serially read during

one operation. At the end of the address space (address

2047), the counter “rolls over” to 0 and the X24C16

continues to output data for each acknowledge re-

ceived. Refer to Figure 9 for the address, acknowledge

and data transfer sequence.

Figure 9. Sequential Read

BUS ACTIVITY:

MASTER

SDA LINE

BUS ACTIVITY:

X24C16

SLAVE

ADDRESS

A

C

K

A

C

K

DATA n+x

S

T

O

P

P

DATA n

A

C

K

DATA n+1

A

C

K

DATA n+2

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Figure 10. Typical System Configuration

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

PULL-UP

RESISTORS

SDA

SCL

VCC

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