X24C16

1

© Xicor, 1991 Patents Pending

Characteristics subject to change without notice

DESCRIPTION

internally organized 2048 X 8. The X24C16 features a

serial interface and software protocol allowing operation

on a simple two wire bus.

The X24C16 is fabricated with Xicor’s advanced CMOS

Textured Poly Floating Gate Technology.

cell providing a minimum endurance of 100,000 cycles

and a minimum data retention of 100 years.

FEATURES

—Active Read Current Less Than 1 mA

—Active Write Current Less Than 3 mA

—Standby Current Less Than 50

—Bidirectional Data Transfer Protocol

—Minimizes Total Write Time Per Byte

—Typical Write Cycle Time of 5 ms

—Endurance: 100,000 Cycles

—Data Retention: 100 Years

Packages

16K

X24C16

2048 x 8 Bit

Preliminary Information

FUNCTIONAL DIAGRAM

3840 FHD F01

START

STOP

LOGIC

CONTROL

LOGIC

SLAVE ADDRESS

REGISTER

+COMPARATOR

H.V. GENERATION

TIMING

& CONTROL

WORD

ADDRESS

COUNTER

XDEC

YDEC

DOUT

ACK

128 X 128

DATA REGISTER

START CYCLE

(8) VCC

R/W

PIN

(4) VSS

(5) SDA

(6) SCL

(3) A2

(2) A1

(1) A0

DOUT

LOAD

INC

CK

8

(7) TEST

3840-1.1 7/29/96 T1/C0/D0 SH