PIC16F722-ESLASHML datasheet(185/302 Pages) MICROCHIP

部品番号	PIC16F722-E/ML

部品情報	28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology

PDF	302 Pages

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メーカー	MICROCHIP [Microchip Technology]

ホームページ	http://www.microchip.com

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185 / 302 page

DS41341E-page 185

PIC16F72X/PIC16LF72X

17.2.10

CLOCK SYNCHRONIZATION

When the CKP bit is cleared, the SCL output is held low

once it is sampled low. therefore, the CKP bit will not

stretch the SCL line until an external I2C master device

has already asserted the SCL line low. The SCL output

will remain low until the CKP bit is set and all other

devices on the I2C bus have released SCL. This

ensures that a write to the CKP bit will not violate the

minimum

high

time

requirement

for

SCL

(Figure 17-14).

17.2.11

SLEEP OPERATION

While in Sleep mode, the I2C module can receive

addresses of data, and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if SSP interrupt is enabled).

FIGURE 17-14:

CLOCK SYNCHRONIZATION TIMING

SDA

SCL

DX-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SSPCON

CKP

Master device

deasserts clock

Master device

asserts clock

PIC16F722-E/ML データシート(PDF) 185 Page - Microchip Technology

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