68HC05CL48 datasheet(3/145 Pages) MOTOROLA

3 / 145 page

June 11, 1997

GENERAL RELEASE SPECIFICATION

MC68HC05CL48

MOTOROLA

REV 2.0

TABLE OF CONTENTS

Section

Page

SECTION 1

GENERAL DESCRIPTION

1.1

FEATURES ...................................................................................................... 1-1

1.2

MCU STRUCTURE.......................................................................................... 1-3

1.3

PIN ASSIGNMENT .......................................................................................... 1-4

1.4

SIGNAL DESCRIPTION .................................................................................. 1-5

1.4.1

VDD and VSS ................................................................................................ 1-5

1.4.2

RESET......................................................................................................... 1-5

1.4.3

IRQ .............................................................................................................. 1-5

1.4.4

IRQ0, IRQ1, IRQ2........................................................................................ 1-6

1.4.5

OSC1, OSC2 ............................................................................................... 1-6

1.4.6

External Clock.............................................................................................. 1-7

1.4.7

PTA0-PTA7.................................................................................................. 1-7

1.4.8

PTB0-PTB7.................................................................................................. 1-7

1.4.9

PTC0-PTC7 ................................................................................................. 1-7

1.4.10

SCK ............................................................................................................. 1-8

1.4.11

MISO, MOSI ................................................................................................ 1-8

1.4.12

SS ................................................................................................................ 1-8

1.4.13

AD0-AD3...................................................................................................... 1-8

1.4.14

TCAP1 ......................................................................................................... 1-8

1.4.15

TCAP2 ......................................................................................................... 1-8

1.4.16

FSK+, FSK–................................................................................................. 1-8

1.4.17

RT_L ............................................................................................................ 1-9

1.4.18

RD1, RD2 .................................................................................................... 1-9

1.4.19

BP0 - BP15 .................................................................................................. 1-9

1.4.20

FP0 - FP44 .................................................................................................. 1-9

1.4.21

VLCD, V0, V1, V2, V3, V4 ........................................................................... 1-9

1.4.22

XFC.............................................................................................................. 1-9

SECTION 2

MEMORY

2.1

MEMORY MAP ................................................................................................ 2-1

2.2

I/O AND CONTROL REGISTERS ................................................................... 2-1

2.2.1

Option Register ($1F) .................................................................................. 2-1

2.3

LCD RAM ......................................................................................................... 2-2

2.4

RAM ................................................................................................................. 2-2

2.5

ROM................................................................................................................. 2-2

2.6

I/O MAPPED REGISTERS .............................................................................. 2-2

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