68HC05CL48 datasheet(46/145 Pages) MOTOROLA

46 / 145 page

GENERAL RELEASE SPECIFICATION

June 11, 1997

MOTOROLA

LOW POWER MODES

MC68HC05CL48

6-2

REV 2.0

6.2

DATA-RETENTION MODE

The contents of RAM and CPU registers are retained at supply voltage as low as

2.0 VDC. This is called the data-retention mode where the data is held, but the

device is not guaranteed to operate. The RESET pin must be held low during

data-retention mode.

To put CPU into data retention mode with the lowest power:

•

Clear OSC_ON bit in OPTION register.

•

Run system with Oscillator clock.

•

Execute STOP instruction to put CPU in STOP mode.

•

Drive RESET pin to logical zero.

•

Lower the VDD voltage. The RESET must remain low continuously

during data retention mode.

To take the CPU out of data retention mode:

•

Return VDD to normal operating level.

•

Return the RESET pin to logical one.

6.3

COP WATCHDOG TIMER CONSIDERATIONS

If the COP Watchdog Timer is selected by setting the enable bit, any execution of

the STOP instruction (either intentional or inadvertent due to the CPU being

disturbed) will be executed as a WAIT instruction. It is because, if a STOP

instruction could be executed, while the COP was enabled. The STOP instruction

will cause the oscillator to halt and prevent the COP Watchdog Timer from timing

out. Therefore, the STOP instruction will put the MCU into WAIT mode, instead of

STOP mode, if COP is enabled.

If the COP Watchdog Timer is selected, the COP will reset the MCU when it times

out. Therefore, it is recommended that the COP Watchdog should be disabled for

a system that must have intentional uses of the WAIT Mode for periods longer

than the COP time-out period.

68HC05CL48 データシート(PDF) 46 Page - Motorola, Inc

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