910GL datasheet(88/426 Pages) INTEL

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Host Bridge/DRAM Controller Registers (D0:F0)

Datasheet

4.1.25

LAC—Legacy Access Control (D0:F0)

PCI Device:

Address Offset:

97h

Default Value:

00h

Access:

R/W

Size:

8 bits

This 8-bit register controls a fixed DRAM hole from 15–16 MB.

Bit

Access &

Default

Description

R/W

Hole Enable (HEN): This field enables a memory hole in DRAM space. The DRAM

that lies "behind" this space is not remapped.

0 = No memory hole.

1 = Memory hole from 15 MB to 16 MB.

6:1

Reserved

R/W

MDA Present (MDAP): This bit works with the VGA Enable bits in the BCTRL

MDA compatible I/O and memory address ranges. This bit should not be set if

device 1's VGA Enable bit is not set.

If device 1's VGA enable bit is not set, then accesses to I/O address range x3BCh–

x3BFh are forwarded to the DMI.

If the VGA enable bit is set and MDA is not present, then accesses to I/O address

range x3BCh–x3BFh are forwarded to PCI Express* if the address is within the

corresponding IOBASE and IOLIMIT, otherwise they are forwarded to the DMI.

MDA resources are defined as the following:

Memory:

0B0000h – 0B7FFFh

I/O:

3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,

(Including ISA address aliases, A [15:10] are not used in decode)

Any I/O reference that includes the I/O locations listed above, or their aliases, will be

forwarded to the DMI even if the reference includes I/O locations not listed above.

The following table shows the behavior for all combinations of MDA and VGA:

VGAEN

MDAP

Description

All References to MDA and VGA space are routed to

the DMI

Illegal combination

All VGA and MDA references are routed to PCI

Express Graphics Attach.

All VGA references are routed to PCI Express

Graphics Attach. MDA references are routed to the

DMI

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