Analog Integrated Circuit Device Data

Freescale Semiconductor

11

33810

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

GENERAL PURPOSE GATE DRIVER PARAMETERS

Short to Battery Fault Detection Filter Timer Accuracy

VDD = High, Outputs Programmed ON

Programmable from 30 µs to 960 µs in replicating increments

Tolerance of timer after using calibration command

Tolerance of timer before using calibration command

-10

-35

+10

+35

%

Output OFF Open Circuit Fault Filter Timer

VDD = 5.0 V, Outputs Off

Tolerance of timer before using calibration command

100

400

µs

PWM Frequency 10 Hz to 1.28 kHz Tolerance after using calibration

command

PWM Frequency 10 Hz to 1.28 kHz Tolerance before using calibration

command

-10%

-35%

10%

35%

Gate Driver Short Fault Duty Cycle

1.0

3.0

%

SPI DIGITAL INTERFACE TIMING(14)

Falling Edge of CS to Rising Edge of SCLK

Required Setup Time

100

–

–

ns

Falling Edge of SCLK to Rising Edge of CS

Required Setup Time

50

–

–

ns

SI to Rising Edge of SCLK

Required Setup Time

16

–

–

ns

Rising Edge of SCLK to SI

Required Hold Time

20

–

–

ns

SI, CS, SCLK Signal Rise Time(15)

–

5.0

–

ns

SI, CS, SCLK Signal Fall Time(16)

–

5.0

–

ns

Time from Falling Edge of CS Low-impedance(17)

–

–

55

ns

Time from Rising Edge off CS to SO High-impedance(18)

–

–

55

ns

Time from Falling Edge of SCLK to SO Data Valid(19)

–

25

55

ns

Sequential Transfer Rate

Time required between data transfers

1.0

–

–

µs

DIGITAL INTERFACE

Calibrated Timer Accuracy

–

–

10

%

Un-calibrated Timer Accuracy

–

–

35

%

Notes

14.

These parameters are guaranteed by design. Production test equipment uses 1.0 MHz, 5.0 V SPI interface.

15.

This parameter is guaranteed by design, however it is not production tested.

16.

Rise and Fall time of incoming SI, CS and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

17.

Time required for valid output status data to be available on SO pin.

18.

Time required for output states data to be terminated at SO pin.

19.

Time required to obtain valid data out from SO following the fall of SCLK with 200 pF load.

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions of 3.0 V

≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 32 V, -40°C ≤ TC ≤ 125°C, and calibrated

timers, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR

= 13 V, TA = 25

°C.

Characteristic

Symbol

Min

Typ

Max

Unit