AFS090 datasheet(47/334 Pages) MICROSEMI

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Fusion Family of Mixed Signal FPGAs

R e visio n 2

2 - 31

No-Glitch MUX (NGMUX)

Positioned downstream from the PLL/CCC blocks, the NGMUX provides a special switching sequence

between two asynchronous clock domains that prevents generating any unwanted narrow clock pulses.

The NGMUX is used to switch the source of a global between three different clock sources. Allowable

inputs are either two PLL/CCC outputs or a PLL/CCC output and a regular net, as shown in Figure 2-24.

The GLMUXCFG[1:0] configuration bits determine the source of the CLK inputs (i.e., internal signal or

GLC). These are set by SmartGen during design but can also be changed by dynamically reconfiguring

the PLL. The GLMUXSEL[1:0] bits control which clock source is passed through the NGMUX to the global

network (GL). See Table 2-13.

Figure 2-24 • NGMUX

Table 2-13 • NGMUX Configuration and Selection Table

GLMUXCFG[1:0]

GLMUXSEL[1:0]

Selected Input

Signal

MUX Type

GLA

2-to-1 GLMUX

GLC

GLA

2-to-1 GLMUX

GLINT

Crystal Oscillator

RC Oscillator

W I/O Ring

CCC/PLL

Clock I/Os

From FPGA Core

PLL/

CCC

GLINT

GLA

GLC

NGMUX

GLMUXCFG[1:0]

PWR UP

GLMUXSEL[1:0]

To Clock Rib Driver

AFS090 データシート(PDF) 47 Page - Microsemi Corporation

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