TNETX15VE datasheet(61/113 Pages) TI1

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TNETX15VE

VLAN-ENGINE ADDRESS-LOOKUP DEVICE

SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

lookup table SRAM allocation

The TNETX15VE uses a 5-bit version of the lookup algorithm described in the previous section. To meet our

duplicate-address support goals, the TNETX15VE extends the lookup to 48 address bits plus two VLAN bits.

In this way, frames with the same address (but different VLANs) are delivered to unique end stations.

When a 5-bit version of the lookup algorithm is used, each address requires 10 tables to store a 50-bit value.

Tables 0 through 9 are used to match the 50 bits involved in the lookup. Table 9 (shown in Figure 11) contains

a pointer to the internal SRAM where the node’s data is contained.

The 16-bit-wide external SRAM is required for proper operation. A 16-bit pointer retrieved from the table coupled

with the next five bits of address being inspected gives a 21-bit (2M) address capability. With the leaves of the

table confined to the internal RAM, there is no value to having more than 512K

× 16 of external SRAM attached

to the TNETX15VE. The algorithm runs out of table leaves before running out of table space if more SRAM is

installed.

Table 9 (in Figure 11) only needs an 11-bit address to reach the table leaf in internal SRAM (only 2K unique

addresses). Since there is only one table-9 entry per active address in the table, some of the information for

a unicast address is stored in the five bits left over. The corresponding bits for a multicast address are not used.

Each table entry requires 40 ns to access and 10 levels total 400 ns towards the lookup time. The internal SRAM

data is accessed in 20 ns. The total time required (400 ns + 20 ns) gives some margin to generate the EAM code

in time for the TNETX3150/TNETX3150A.

An allocated (but unused) table entry is set to 0 since 0 cannot be a valid address for a table leaf.

Table 0 (Root)

Table 1

Table 2

Table 3

Table 4

Table 5

Table 6

Table 7

Table 8

Table 9

Internal SRAM Data

Bit 47–43

Bit 42–38

Bit 37–33

Bit 32–28

Bit 27–23

Bit 22–18

Bit 17–33

Bit 12–8

Bit 7–3

Bit 2–0 + VLAN (2 Bits)

Figure 11. Address Tables

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