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JS28F256P33BFE データシート(PDF) 38 Page - Micron Technology

部品番号 JS28F256P33BFE
部品情報  NumonyxTM StrataFlash Embedded Memory
PDF  90 Pages
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メーカー  MICRON [Micron Technology]
ホームページ  http://www.micron.com
Logo MICRON - Micron Technology

JS28F256P33BFE データシート(HTML) 38 Page - Micron Technology

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P33-65nm
Datasheet
Aug 2009
38
Order Number: 320003-08
Table 13: End of Wordline Data and WAIT state Comparison
11.1.4
WAIT Polarity
The WAIT Polarity bit (WP), RCR.10 determines the asserted level (VOH or VOL) of WAIT.
When WP is set, WAIT is asserted high. When WP is cleared, WAIT is asserted low
(default). WAIT changes state on valid clock edges during active bus cycles (CE#
asserted, OE# asserted, RST# deasserted).
11.1.5
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR.15=0). The WAIT signal is only “deasserted” when data is valid on the bus.
When the device is operating in synchronous non-array read mode, such as read
status, read ID, or read query. The WAIT signal is also “deasserted” when data is valid
on the bus.
WAIT behavior during synchronous non-array reads at the end of word line works
correctly only on the first data access.
When the device is operating in asynchronous page mode, asynchronous single word
read mode, and all write operations, WAIT is set to a deasserted state as determined
by RCR.10. See Figure 18, “Asynchronous Single-Word Read (ADV# Latch)” on
page 52, and Figure 19, “Asynchronous Page-Mode Read Timing” on page 52.
Latency Count
P33-130nm
P33-65nm
Data States
WAIT States
Data States
WAIT States
1
Not Supported
Not Supported
Not Supported
Not Supported
2
4
0 to 1
Not Supported
Not Supported
3
4
0 to 2
16
0 to 2
4
4
0 to 3
16
0 to 3
5
4
0 to 4
16
0 to 4
6
4
0 to 5
16
0 to 5
7
4
0 to 6
16
0 to 6
8
Not Supported
Not Supported
16
0 to 7
9
16
0 to 8
10
16
0 to 9
11
16
0 to 10
12
16
0 to 11
13
16
0 to 12
14
16
0 to 13
15
16
0 to 14



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