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LT1956IGN データシート(PDF) 16 Page - Linear Technology |
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LT1956IGN データシート(HTML) 16 Page - Linear Technology |
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16 / 28 page ![]() 16 LT1956/LT1956-5 1956f bypassed with a 1000pF capacitor to prevent coupling problems from the switch node. If hysteresis is desired in the undervoltage lockout point, a resistor RFB can be added to the output node. Resistor values can be calcu- lated from: R RV V V V RA RR V V HI LO IN OUT LO FB HI OUT = −+ ()+ [] − () = () () 238 1 238 5 5 ./ .. / ∆∆ ∆ µ 25k suggested for RLO VIN = Input voltage at which switching stops as input voltage descends to trip level ∆V = Hysteresis in input voltage level Example: output voltage is 5V, switching is to stop if input voltage drops below 12V and should not restart unless input rises back to 13.5V. ∆V is therefore 1.5V and VIN = 12V. Let RLO = 25k. R k kA k k Rk k HI FB = −+ ()+ [] µ () = () = = ()= 25 12 2 38 1 5 5 1 1 5 238 25 5 5 25 10 41 224 116 116 5 1 5 387 .. / . .– . . . /. SYNCHRONIZING The SYNC input must pass from a logic level low, through the maximum synchronization threshold with a duty cycle between 10% and 90%. The input can be driven directly from a logic level output. The synchronizing range is equal to initial operating frequency up to 700kHz. This means that minimum practical sync frequency is equal to the worst-case high self-oscillating frequency (570kHz), not the typical operating frequency of 500kHz. Caution should be used when synchronizing above 662kHz because at higher sync frequencies the amplitude of the internal slope compensation used to prevent subharmonic switching is reduced. This type of subharmonic switching only occurs at input voltages less than twice output voltage. Higher inductor values will tend to eliminate this problem. See Frequency Compensation section for a discussion of an entirely different cause of subharmonic switching before assuming that the cause is insufficient slope compensa- tion. Application Note 19 has more details on the theory of slope compensation. At power-up, when VC is being clamped by the FB pin (see Figure 2, Q2), the sync function is disabled. This allows the frequency foldback to operate in the shorted output con- dition. During normal operation, switching frequency is controlled by the internal oscillator until the FB pin reaches 0.8V, after which the SYNC pin becomes operational. If no synchronization is required, this pin should be connected to ground. APPLICATIO S I FOR ATIO – + – + 2.38V 0.4V GND VSW LT1956 INPUT RFB L1 RHI 1956 F04 OUTPUT C1 SHDN STANDBY IN TOTAL SHUTDOWN 5.5 µA RLO C2 + Figure 4. Undervoltage Lockout |
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