LT1956IGN datasheet(6/28 Pages) LINER

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LT1956/LT1956-5

1956f

VC (Pin 11) The VC pin is the output of the error amplifier

and the input of the peak switch current comparator. It is

normally used for frequency compensation, but can also

serve as a current clamp or control loop override. VC sits

at about 1V for light loads and 2V at maximum load. It can

be driven to ground to shut off the regulator, but if driven

high, current must be limited to 4mA.

FB/SENSE (Pin 12): The feedback pin is used to set the

output voltage using an external voltage divider that gen-

erates 1.22V at the pin for the desired output voltage. The

5V fixed output voltage parts have the divider included on

the chip and the FB pin is used as a SENSE pin, connected

directly to the 5V output. Three additional functions are

performed by the FB pin. When the pin voltage drops

below 0.6V, switch current limit is reduced and the exter-

nal SYNC function is disabled. Below 0.8V, switching

frequency is also reduced. See Feedback Pin Functions in

Applications Information for details.

SYNC (Pin 14): The SYNC pin is used to synchronize the

internal oscillator to an external signal. It is directly logic

compatible and can be driven with any signal between

10% and 90% duty cycle. The synchronizing range is

equal to initial operating frequency up to 700kHz. See

Synchronizing in Applications Information for details. If

unused, this pin should be tied to ground.

SHDN (Pin 15): The SHDN pin is used to turn off the

regulator and to reduce input current to a few microam-

peres. This pin has two thresholds: one at 2.38V to disable

switching and a second at 0.4V to force complete mi-

cropower shutdown. The 2.38V threshold functions as an

accurate undervoltage lockout (UVLO); sometimes used

to prevent the regulator from delivering power until the

input voltage has reached a predetermined level.

If the SHDN pin functions are not required, the pin can

either be left open (to allow an internal bias current to lift

the pin to a default high state) or be forced high to a level

not to exceed 6V.

GND (Pins 1, 8, 9, 16): The GND pin connections act as

the reference for the regulated output, so load regulation

will suffer if the “ground” end of the load is not at the same

voltage as the GND pins of the IC. This condition will occur

when load current or other currents flow through metal

paths between the GND pins and the load ground. Keep the

paths between the GND pins and the load ground short

and use a ground plane when possible. For the FE package,

the exposed pad should be soldered to the copper GND

plane underneath the device. (See Applications Informa-

tion—Layout Considerations.)

SW (Pin 2): The switch pin is the emitter of the on-chip

power NPN switch. This pin is driven up to the input pin

voltage during switch on time. Inductor current drives the

switch pin negative during switch off time. Negative volt-

age is clamped with the external catch diode. Maximum

negative switch voltage allowed is – 0.8V.

NC (Pins 3, 5, 7, 13): No Connection.

VIN (Pin 4): This is the collector of the on-chip power NPN

switch. VIN powers the internal control circuitry when a

voltage on the BIAS pin is not present. High dI/dt edges

occur on this pin during switch turn on and off. Keep the

path short from the VIN pin through the input bypass

capacitor, through the catch diode back to SW. All trace

inductance on this path will create a voltage spike at switch

off, adding to the VCE voltage across the internal NPN.

BOOST (Pin 6): The BOOST pin is used to provide a drive

voltage, higher than the input voltage, to the internal

bipolar NPN power switch. Without this added voltage, the

typical switch voltage loss would be about 1.5V. The

additional BOOST voltage allows the switch to saturate

and voltage loss approximates that of a 0.2

Ω FET struc-

ture, but with much smaller die area.

BIAS (Pin 10): The BIAS pin is used to improve efficiency

when operating at higher input voltages and light load

current. Connecting this pin to the regulated output volt-

age forces most of the internal circuitry to draw its oper-

ating current from the output voltage rather than the input

supply. This architecture increases efficiency especially

when the input voltage is much higher than the output.

Minimum output voltage setting for this mode of operation

is 3V.

PI FU CTIO S

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