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LT1956/LT1956-5

1956f

APPLICATIO S I FOR ATIO

LAYOUT CONSIDERATIONS

As with all high frequency switchers, when considering

layout, care must be taken in order to achieve optimal

electrical, thermal and noise performance. For maximum

efficiency, switch rise and fall times are typically in the

nanosecond range. To prevent noise both radiated and

conducted, the high speed switching current path, shown

in Figure 5, must be kept as short as possible. This is

implemented in the suggested layout of Figure 6. Shorten-

ing this path will also reduce the parasitic trace inductance

of approximately 25nH/inch. At switch off, this parasitic

inductance produces a flyback spike across the LT1956

switch. When operating at higher currents and input

voltages, with poor layout, this spike can generate volt-

ages across the LT1956 that may exceed its absolute

maximum rating. A ground plane should always be used

under the switcher circuitry to prevent interplane coupling

and overall noise.

The VC and FB components should be kept as far away as

possible from the switch and boost nodes. The LT1956

pinout has been designed to aid in this. The ground for

these components should be separated from the switch

current path. Failure to do so will result in poor stability or

subharmonic like oscillation.

Figure 6. Suggested Layout

GND

SHDN

SYNC

GND

BOOST

VIN

PLACE FEEDTHROUGH AROUND

GROUND PINS (4 CORNERS) FOR

GOOD THERMAL CONDUCTIVITY

LT1956

1956 F06

CFB

MINIMIZE LT1956

C3-D1 LOOP

GND

BIAS

CONNECT TO

GROUND PLANE

KELVIN SENSE

VOUT

KEEP FB AND VC COMPONENTS

AWAY FROM HIGH FREQUENCY,

HIGH CURRENT COMPONENTS

GND

VOUT

VIN

FOR THE FE PACKAGE,

SOLDER THE EXPOSED

PAD TO THE COPPER

GROUND PLANE

UNDERNEATH THE DEVICE

1956 F05

VIN

LT1956

HIGH

FREQUENCY

CIRCULATING

PATH

LOAD

Figure 5. High Speed Switching Path

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