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STM8L151F3P6 データシート(PDF) 79 Page - STMicroelectronics |
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STM8L151F3P6 データシート(HTML) 79 Page - STMicroelectronics |
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79 / 112 page  STM8L151x2, STM8L151x3 Electrical parameters Doc ID 018780 Rev 4 79/112 Figure 31. Typical NRST pull-up current Ipu vs VDD The reset network shown in Figure 32 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max. level specified in Table 38. Otherwise the reset is not taken into account internally. For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If the NRST signal is used to reset the external circuitry, attention must be paid to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. The minimum recommended capacity is 10 nF. Figure 32. Recommended NRST pin configuration 0 20 40 60 80 100 120 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 VDD [V] -40°C 25°C 90°C 130°C EXTERNAL RESET CIRCUIT STM8 Filter RPU VDD INTERNAL RESET NRST 0.1 µF (Optional) |
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