STM8L151F3P6 datasheet(98/112 Pages) STMICROELECTRONICS

98 / 112 page

Option bytes

STM8L151x2, STM8L151x3

98/112

Doc ID 018780 Rev 4

Table 56.

Option byte description

Option

byte

No.

Option description

OPT0

ROP[7:0] Memory readout protection (ROP)

0xAA: Disable readout protection (write access via SWIM protocol)

Refer to Readout protection section in the STM8L15x and STM8L16x reference manual (RM0031).

OPT1

UBC[7:0] Size of the user boot code area

0x00: UBC is not protected.

0x01: Page 0 is write protected.

0x02: Page 0 and 1 reserved for the UBC and write protected. It covers only the interrupt vectors.

0x03: Page 0 to 2 reserved for UBC and write protected.

0x7F to 0xFF - All 128 pages reserved for UBC and write protected.

The protection of the memory area not protected by the UBC is enabled through the MASS keys.

Refer to User boot code section in the STM8L15x and STM8L16x reference manual (RM0031).

OPT2

Reserved

OPT3

IWDG_HW: Independent watchdog

0: Independent watchdog activated by software

1: Independent watchdog activated by hardware

IWDG_HALT: Independent window watchdog off on Halt/Active-halt

0: Independent watchdog continues running in Halt/Active-halt mode

1: Independent watchdog stopped in Halt/Active-halt mode

WWDG_HW: Window watchdog

0: Window watchdog activated by software

1: Window watchdog activated by hardware

WWDG_HALT: Window window watchdog reset on Halt/Active-halt

0: Window watchdog stopped in Halt mode

1: Window watchdog generates a reset when MCU enters Halt mode

OPT4

HSECNT: Number of HSE oscillator stabilization clock cycles

0x00 - 1 clock cycle

0x01 - 16 clock cycles

0x10 - 512 clock cycles

0x11 - 4096 clock cycles

LSECNT: Number of LSE oscillator stabilization clock cycles

0x00 - 1 clock cycle

0x01 - 16 clock cycles

0x10 - 512 clock cycles

0x11 - 4096 clock cycles

Refer to Table 28: LSE oscillator characteristics on page 67.

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