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HM5259165B データシート(PDF) 49 Page - Elpida Memory

部品番号 HM5259165B
部品情報  512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 횞 16-bit 횞 4-bank/16-Mword 횞 8-bit 횞 4-bank /32-Mword 횞 4-bit 횞 4-bank PC/133, PC/100 SDRAM
PDF  63 Pages
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メーカー  ELPIDA [Elpida Memory]
ホームページ  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

HM5259165B データシート(HTML) 49 Page - Elpida Memory

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HM5259165B/HM5259805B/HM5259405B-75/A6
Data Sheet E0118H10
49
Notes: 1. I
CC depends on output load condition when the device is selected.
I
CC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. After self refresh mode set, self refresh current.
9. Input signals are V
IH or VIL fixed.
Capacitance (Ta = 25°C, V
CC, VCCQ = 3.3 V ± 0.3 V)
Parameter
Symbol
Min
Max
Unit
Notes
Input capacitance (CLK)
C
I1
2.5
7
pF
1, 2, 4
Input capacitance (Input)
C
I2
2.5
7
pF
1, 2, 4
Output capacitance (DQ)
C
O
4
8
pF
1, 2, 3, 4
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
3. DQM, DQMU/DQML = V
IH to disable Dout.
4. This parameter is sampled and not 100% tested.



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