Reset

AN4092

32/38

Doc ID 023080 Rev 2

Table 7.

Reset source description

Reset

SRAM

Registers

(including

PLL, etc.)

PORT

PIN

BA

M

WKPCFG,

PLLREF,

BOOTCFG

Factory

trimming

Shadow

information

(NVUSR0,

Lock

Registers,

etc.)

POR/LVI

Rando

m

content

/

Retenti

on not

reliable

XX

Not

affected

Reset

state

as per

signal

proper

ties

table

(5)

Exec

uted

Sampled

Trimming

reloaded

from Flash

Reloaded from

Flash

ER / LLR /

LCR /

WTDR /

JTAG

Reset /

SSR

Content

unaffect

ed

Not

affected

Not

affected

Reset

state

as per

signal

proper

ties

table

(7)

Exec

uted

Sampled

Trimming

kept

Reloaded from

Flash

SER

Content

unaffect

ed

Not

affected

Not

affected

Not

affected

Not

affect

ed

Not

exec

uted

Not Sampled

Trimming

kept

Not reloaded

from Flash

1.

POR: Power-on Reset / LVI: Low Voltage Inhibit / ER: External Reset / LLR: Loss of Lock Reset / LCR: Loss of Clock Reset

/ WTDR: Watchdog Timer/Debug Reset / SSR: Software System Reset / SER: Software External Reset

2.

JCOMP is used to reset JTAG Controller

3.

Including MCR register

4.

Provided that the supply voltages are within the limits

5.

Refer to RM / DS

6.

RAM content unaffected (CAN message buffer, ETPU memories, etc.)

7.

Refer to RM / DS