AN4068 datasheet(44/63 Pages) STMICROELECTRONICS

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Design guidelines

AN4068

44/63

Doc ID 022923 Rev 2

An array of 4 x 4 thermal vias at 1.0 mm pitch, with a via diameter of 0.3 mm, has been

incorporated into the thermal pad, as shown in Figure 35.

To minimize the solder wicking effect due to open vias, possibly leading to poor soldering of

the QFN48 exposed pad, the via encroaching technique has been adopted (see bottom-side

image in Figure 35). The bottom-side solder resist has only small openings (nearly 0.2 mm

larger than the via drill diameter) around the vias; the reduced area of exposed copper on

the bottom reduces the amount of solder paste flowing down the vias.

Figure 35.

PCB copper dissipating area on top layer (left) and bottom layer (right) for

the ST7580 reference design board

Another important parameter for effective heat dissipation is the copper thickness for both

top and bottom layers. 1 oz copper is considered as the minimum value to ensure good

dissipation.

The bottom-side routing plays an important role too. The solid ground area of copper under

the device must be as large as possible to minimize the thermal impedance. Therefore,

traces on the bottom side must run as far as possible from the device area.

9.1.2

Ground connections

Good soldering of the ST7580 exposed pad is required also to minimize ground noise.

Being the exposed pad connected to VSSA, its cleanliness is directly related to the noise

level detected by the receiving circuitry (i.e. to the actual sensitivity level) and to the PLL

behavior.

It is very important to filter each supply pin to its respective ground: VCC to VSS, VCCA and

VDD_PLL to VSSA, VDDIO and VDD to GND.

9.2

Thermal impedance and power dissipation calculation

The relationship between junction temperature (TJ) and power dissipation during

transmission (PD) is described by the following formula:

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