AN4192 datasheet(31/47 Pages) STMICROELECTRONICS

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AN4192

Low-side FET selection

Doc ID 023820 Rev 1

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Due to the above mentioned issue, in most VRM applications, one common design

guideline is to reduce the total gate resistance.

Figure 35.

Low ext. RG (2

Ω) LS FET waveforms during HS turn-on

Increasing RG,LS(EXT), there are three main effects on the LS switching behavior:

●

A higher induced voltage appears between gate and source (7) (see Figure 36).

●

Longer VGS, LS fall time (130 ns vs. 83 ns), due to the input time constant enlargement

(the LS VGS bounces before reaching zero level).

●

Phase node overshoot reduction, because of the intrinsic LS slow-down.

Figure 36.

High ext. RG (4.7

Ω) LS FET waveforms during HS turn-on

Generally, the higher the RG,LS(EXT), the lower the efficiency, due to bigger gate drive losses.

In particular, the efficiency loss is much higher when more LS FETs are paralleled or bigger

die size devices are used (more capacitances to be switched on/off). For the above

mentioned issues, typically, the more common RG,LS(EXT) values are 0 - 2.2 Ω.

In the same way, by increasing the LS intrinsic gate resistance (RG,LS(EXT)), the spurious

gate-source voltage tends to grow (see Figure 37 and 38).

AM16478V1

AM16479V1

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