AN1105 datasheet(13/100 Pages) STMICROELECTRONICS

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ST7 pCAN PERIPHERAL DRIVER

– Two 11-bit filters and two 11-bit masks are used for hardware filtering with identifier/iden-

tifier-range definition. The masks define which bits of the filters are to be ignored and which

are to be tested. Any message whose identifier does not match will not be saved in the buff-

ers.

– The cell automatically enters Low Power mode after the reception of 20 recessive bits, or

Standby state on command.

– The pCAN peripheral can wake-up the ST7 microcontroller from HALT mode. See Section

2.1.3.2 "Waking-up from HALT Mode" to learn how.

– The CAN Error Confinement feature, as defined by the CAN protocol, is fully implement-

ed, with read-only access to the counters and maskable interrupts on state changes. Once

in Bus Off state, the cell automatically returns to Bus Active state if it has detected 128x11

recessive bits on the bus (see Section 2.1.3.1 "Controlling Status Changes"). See note on

Section 2.1.3.2 "Waking-up from HALT Mode" to see how the driver can provide you with full

control over the bus-off to bus-active transition.

– The three Send/Receive buffers, filters, masks and counters are mapped at a unique ad-

dress space, allowing efficient software access.

1.6.2 Cell Behaviour

In Standby state, the node monitors the bus in order to detect a dominant pulse that could gen-

erate an interrupt (See ST72511 datasheet p.112, Interrupt Control Register, SCIE bit).

When the RUN bit of the Control Status Register is set (See ST72511 datasheet p.113), the

cell leaves

standby mode. It then enters resynchronization mode before it really starts running.

If the WKPS bit of the Control/Status Register is set, then the cell will send a dominant pulse

when it wakes up. You can choose between two resynchronization durations: 11 recessive

bits if the FSYN bit of the CSR is set or 128*11 recessive bits if not (See ST72511 datasheet

p.113).

If the cell resynchronizes after leaving bus-off state, it will wait 128*11 recessive bits, whatever

the value of FSYN may be.

To send data, a buffer has to be selected first by writing to the Page Selection Register (See

datasheet p. 114). Then it has to be locked for transmission by setting the LOCK bit in the

Buffer Control/Status Register (See datasheet p.116: LOCK bit and RDY bit). Then data can

be written in the buffer registers: identifier, data length code, data bytes. Writing in the seventh

data register starts transmission.

Received data is automatically stored in one of the buffers configured for reception (LOCK bit

reset) each time a message identifier matches the hardware filters of the pCAN cell, and pro-

vided that this buffer is marked as free (RDY bit reset. See datasheet p.116: LOCK bit and

RDY bit). The masks/filters can be configured through the Filter/Mask High/Low Registers

(See datasheet p.117).

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