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UPD703003 データシート(PDF) 54 Page - NEC |
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UPD703003 データシート(HTML) 54 Page - NEC |
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54 / 82 page ![]() µPD703003 54 Data Sheet U12261EJ2V1DS00 Recommended Operating Conditions Operation Mode Internal Operating Operating Ambient Power Supply Clock Frequency ( φ) Temperature (TA) Voltage (VDD) Direct mode 0 to 33 MHzNote 1 –40 to +85 °C 5.0 V ±10% 5 to 33 MHzNote 2 –40 to +85 °C 5.0 V ±10% PLL mode Free-running oscillation frequency to 33 MHz –40 to +85 °C 5.0 V ±10% Notes 1. When not using A/D converter 2. When using A/D converter Remark The range of internal operating clock frequency in PLL mode is the assured range of function operation. PLL locked frequency is specified by tCYX. Recommended Oscillator (a) Ceramic oscillation resonator connection (TA = –40 to +85 °C) X1 X2 C1 C2 Oscillation Recommended Circuit Oscillation Voltage Oscillation Stabilization Manufacturer Part Number Frequency Constant Range Time (MAX.) fXX (MHz) C1 (pF) C2 (pF) MIN. (V) MAX. (V) TOST (ms) TDK CCR5.0MC3 5.0 On-chip On-chip 4.5 5.5 0.36 FCR5.0MC5 5.0 On-chip On-chip 4.5 5.5 0.32 CCR6.6MC3 6.6 On-chip On-chip 4.5 5.5 0.28 Murata Mfg. CSA5.00MG040 5.0 100 100 4.5 5.5 0.46 CST5.00MGW040 5.0 On-chip On-chip 4.5 5.5 0.46 CSA6.60MTZ040 6.6 100 100 4.5 5.5 0.42 CST6.60MTW040 6.6 On-chip On-chip 4.5 5.5 0.42 Cautions 1. Set the oscillator as close to the X1 and X2 pins as possible. 2. No other signal lines should be wired in the area enclosed by broken lines. 3. When matching µPD703003 with a resonator, be sure to perform sufficient evaluation. |
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