RM0312 datasheet(144/275 Pages) STMICROELECTRONICS

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16-bit general purpose timer (TIM2/TIM3)

RM0312

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DocID022352 Rev 3

17.7

TIMx registers

17.7.1

Control register 1 (TIMx_CR1)

Address offset: 0x00

Reset value: 0x00

654

3210

ARPE

CMS[1:0]

DIR

OPM

URS

UDIS

CEN

Bit 7 ARPE: Auto-Reload Preload Enable

0: TIMx_ARR register is not buffered through a preload register. It can be written directly.

1: TIMx_ARR register is buffered through a preload register.

Bits 6:5 CMS: Center-aligned Mode Selection

00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).

01: Center-aligned mode 1. The counter counts up and down alternately. Output compare interrupt

flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the

counter is counting down.

10: Center-aligned mode 2. The counter counts up and down alternately. Output compare interrupt

flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the

counter is counting up.

11: Center-aligned mode 3. The counter counts up and down alternately. Output compare interrupt

flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the

counter is counting up or down.

Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the

counter is enabled (CEN=1)

Encoder mode (SMS=001, 010 or 011 in GPT_SMCR register) must be disabled in center-

aligned mode.

Bit 4 DIR: Direction

0: Counter used as up-counter.

1: Counter used as down-counter.

Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.

Bit 3 OPM: One Pulse Mode

0: Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the CEN bit )

Bit 2 URS: Update Request Source

0: When enabled, an update interrupt request is sent as soon as registers are updated (counter

overflow)

1: When enabled, an update interrupt request is sent only when the counter reaches the overflow.

Bit 1 UDIS: Update Disable

0: An Update event is generated as soon as a counter overflow occurs or a software update is

generated or an hardware reset is generated by the clock/trigger mode controller. Buffered registers

are then loaded with their preload values

1: An Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). The

counter and the prescaler are re-initialized if the UG bit is set .

Bit 0 CEN: Counter Enable

0: Counter disabled

1: Counter enabled

RM0312 データシート(PDF) 144 Page - STMicroelectronics

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