RM0312 datasheet(145/275 Pages) STMICROELECTRONICS

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RM0312

16-bit general purpose timer (TIM2/TIM3)

170

17.7.2

Control register 2 (TIMx_CR2)

Address offset: 0x01

Reset value: 0x00

654

3210

Reserved

MMS[2:0]

Reserved

Bit 7 Reserved

Bits 6:4 MMS: Master mode selection

These bits select the information to be sent in master mode to other timers for synchronization

(TRGO). The combination is as follows:

000: Reset - the UG bit from the TIM3_EGR register is used as trigger output (TRGO). If the reset is

generated by the trigger input (clock/trigger mode controller configured in trigger reset mode) then

the signal on TRGO is delayed compared to the actual reset.

001: Enable - the Counter Enable signal is used as trigger output (TRGO). It is used to start several

timers at the same time or to control a window in which a slave timer is enabled. The Counter

Enable signal is generated by a logic OR between CEN control bit and the trigger input when

configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is

a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in

TIM3_SMCR register).

010: Update - The update event is selected as trigger output (TRGO).

011: Reserved

100: Reserved

101: Reserved

111: Reserved

Bits 3:0 Reserved

RM0312 データシート(PDF) 145 Page - STMicroelectronics