RM0312 datasheet(146/275 Pages) STMICROELECTRONICS

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16-bit general purpose timer (TIM2/TIM3)

RM0312

146/275

DocID022352 Rev 3

17.7.3

Slave mode control register (TIMx_SMCR)

Address offset: 0x02

Reset value: 0x00

654

3210

MSM

TS[2:0]

Reserved

SMS[2:0]

Bit 7 MSM: Master/slave mode

0: No action

1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization

between timers (through TRGO).

Bits 6:4 TS[2:0]: Trigger selection

This bit-field selects the trigger input to be used to synchronize the counter.

000: Internal trigger ITR0 connected to TIM4 TRGO

001: Reserved

010: Internal trigger ITR2 connected to TIM3 TRGO

011: Internal trigger ITR3 connected to TIM2 TRGO

100: TI1 Edge Detector (TI1F_ED)

101: Filtered Timer Input 1 (TI1FP1)

110: Filtered Timer Input 2 (TI2FP2)

111: External Trigger input (ETRF)

Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong

edge detections at the transition.

Bit 3 Reserved

Bits 2:0 SMS[2:0]: Clock/trigger/slave mode selection

When external signals are selected, the active edge of the trigger signal (TRGI) is linked to the polarity

selected on the external input (see Input Control register and Control register description).

000: Clock/trigger controler disabled - if CEN = ‘1’ then the prescaler is clocked directly by the

internal clock.

001: Reserved

010: Reserved

011: Reserved

100: Trigger reset mode - Rising edge of the selected trigger signal (TRGI) reinitializes the counter

and generates an update of the registers.

101: Gated Mode - The counter clock is enabled when the trigger signal (TRGI) is high. The counter

stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are

controlled.

110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only

the start of the counter is controlled.

111: External clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

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