Power consumption comparison

AN4635

18/34

DocID027290 Rev 1

6.4

Going to Stop between received bytes

The LPUARTs ability to wake from Stop on external event leads to possibility to enter the

Stop mode even during pause between bytes in reception phase.

The best results comes with operational speeds slightly below the limit of voltage regulator

range 3, specifically 4 MHz MSI clock. In this way the interrupt overhead time is very short

and the MCU spends most of the time in Stop mode.

Lower speeds actually lead to slightly higher power consumption during reception. The

difference is not big, just around 10%. Yet still using polling and very slow clock setting the

power consumption can be even lower than this, but sacrificing the flexibility of serving any

other tasks.

Table 6. Configurations - Interrupt operation

Curve in Figure 4

Black

Red

Idle mode between

transmissions

Stop

JTAG interface

OFF

Current average

over phases 2, 3 and 4

14.47 µA

9.75 µA

Clock

250 kHz MSI

Voltage regulator

Range 3

AHB/APB ratio

1/1

ULP/FWU

+/+

Baud rate

9600

SW used

Interrupt operation (Com IT)

with defines RXSLEEP

and TXSLEEP

Blocking operation (Com Polling)

with defines RXSLEEP

and TXSLEEP