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SM5843AS1 データシート(PDF) 4 Page - Nippon Precision Circuits Inc

部品番号 SM5843AS1
部品情報  Audio Multi-function Digital Filter
PDF  24 Pages
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メーカー  NPC [Nippon Precision Circuits Inc]
ホームページ  http://www.npc.co.jp/en
Logo NPC - Nippon Precision Circuits Inc

SM5843AS1 データシート(HTML) 4 Page - Nippon Precision Circuits Inc

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SM5843A
×1
NIPPON PRECISION CIRCUITS—4
PIN DESCRIPTION
Number
Name
I/O1
Description
1
DI/INF2N
Ip
Data input when INF1N is LOW, and input format select pin when INF1N is HIGH.
2
BCKI
Ip
Input bit clock
3
CKSLN
Ip
Oscillator and system clock select input. 384fs when HIGH, and 256fs when LOW.
4
INF1N
Ip
Input format select pin. INF1N and INF2N select the pin functions below.
5
IW1N/DIL
Ip
Input bit length select pin when INF1N is LOW, and left-channel data input when INF1N is HIGH.
IW1N and IW2N select the input data length.
6
XTI
I
Oscillator input connection
7
XTO
O
Oscillator output connection
8
VSS
Ground
9
CKO
O
Oscillator output clock. Same frequency as XTI.
10
IW2N/DIR
Ip
Input bit length select pin when INF2N is LOW, and right-channel data input when INF2N is HIGH.
IW1N and IW2N select the input data length as shown in the table for pin 5.
11
MDT
Ip
Attenuator serial data input
12
MCK
Ip
Attenuator bit clock input
13
MLEN
Ip
Attenuator latch enable input
14
RSTN
Ip
System reset. Reset operation when LOW, and normal operation when HIGH.
15
MUTE
Ip
Mute control signal. Muting when HIGH, and normal operation when LOW.
16
DEMP
Ip
Deemphasis control signal. OFF when LOW, and ON when HIGH.
17
FSEL1
Ip
Deemphasis filter select inputs
18
FSEL2
Ip
19
OW20N
Ip
Output bit length select pin. 20-bit output when LOW, and 18-bit output when HIGH.
20
SYNCN
Ip
Sync mode select pin. Normal sync mode when LOW, and jitter-free mode when HIGH.
21
TMOD1
Ip
Dither processing control. ON when LOW, and OFF when HIGH.
22
VDD
5 V supply
INF1N
DI/INF2N
Input format
Pin function selection
DI/INF2N
IW1N/DIL
IW2N/DIR
LOW
LOW
LR alternating, trailing data
DI
IW1N
IW2N
LOW
HIGH
HIGH
LOW
LR alternating, leading data
INF2N
DIL
DIR
HIGH
HIGH
LR simultaneous, leading data
INF1N
IW2N/DIL
IW1N/DIR
Input bit length
LOW
LOW
LOW
20 bits
LOW
HIGH
20 bits
HIGH
LOW
18 bits
HIGH
HIGH
16 bits
HIGH
××
20 bits
FSEL1
FSEL2
Sampling frequency (fs)
LOW
LOW
44.1 kHz
LOW
HIGH
48 kHz
HIGH
LOW
Test mode
HIGH
HIGH
32 kHz



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