SM5843A

×1

NIPPON PRECISION CIRCUITS—19

TIMING DIAGRAMS

Input Timing Examples (DIN, BCKI, LRCI)

Figure 7. LR alternating, trailing data, 16-bit input

Data after lsb (bit 20) is ignored. After bit 20, BCKI clock input is not needed.

Figure 8. LR alternating, leading data, 20-bit input

Data after lsb (bit20) is ignored. After bit 20, BCKI clock input is not needed.

Figure 9. LR simultaneous, leading data, 20-bit input

1

2

14 15 16

1

2

14 15 16

DI

BCKI

LRCI

(MSB)

(LSB)

(MSB)

(LSB)

Lch DATA

Rch DATA

1 / fs

19 20

DIL

BCKI

LRCI

(MSB)

(LSB)

(MSB)

(LSB)

Lch DATA

Rch DATA

1 / fs

12

3

19 20

12

3

1

DIR

DIL

BCKI

LRCI

(MSB)

(LSB)

(LSB)

Lch DATA

1 / fs

12

3

1

DIR

45

6

19 20

18

123

1

4

5

6

19 20

18

Rch DATA

(MSB)