SM5844AF

NIPPON PRECISION CIRCUITS—4

PIN DESCRIPTION

Name

Description

1, 2

DI

Ip

Data input

3, 4

BCKI

Ip

Input bit clock

5

Ip

Input word clock (fsi)

6

ICLK

I

Input system clock input

7

ICKSL

Ip

Input system clock (ICLK) select. 384fsi when HIGH, and 256fsi when LOW .

8, 9

IFM1

Ip

Input format select

10, 11

IFM2

Ip

12, 13

V D D

–

5 V supply pin

14, 15

DMUTE

Ip

Direct mute pin

1 6

MCOM

Ip

Interface switch control pin. M D T, MCK and MLEN control when HIGH. FSI1, FSI2 and DEEM

control when LOW .

17

MDT/FSI1

Ip

When MCOM is HIGH: Microcontroller interface

data input (MDT)

When MCOM is LOW : Deemphasis frequency

set pins

1 8

MCK/FSI2

Ip

When MCOM is HIGH: Microcontroller interface

bit clock (MCK)

19, 20

MLEN/DEEM

Ip

When MCOM is HIGH: Microcontroller data word latch clock (MLEN)

When MCOM is LOW : Deemphasis ON/OFF control (DEEM)

21, 22

O W18N

Ip

Output format select

When IISN = HIGH (nor mal mode)

When IISN = LOW (IIS mode)

23, 24

O W20N

Ip

25, 26

IISN

Ip

IIS output mode select. Nor mal mode when HIGH, and IIS mode when LOW .

2 7

S TAT E

O

Internal operation status output (for operation check)

2 8

TST1N

Ip

Output dither control. Dither ON when LOW , and OFF when HIGH.

2 9

TST2N

Ip

Test pin. Test mode when LOW . Nor mal operating mode when HIGH.

IFM1

IFM2

W ord length

Data sequence

Data position

L O W

L O W

16 bits

MSB first

Rear packe d

L O W

HIGH

20 bits

HIGH

L O W

Front packe d

HIGH

HIGH

LSB first

Rear packe d

FSI1

FSI2

fsi

L O W

HIGH

48.0 kHz

×

L O W

44.1 kHz

HIGH

HIGH

32.0 kHz

O W20N

O W18N

W ord length

Data position

LO W

L O W

20 bits

Front packe d

L O W

HIGH

Rear packe d

HIGH

L O W

18 bits

HIGH

HIGH

16 bits

O W20N

O W18N

W ord length

Data position

LO W

L O W

20 bits

IIS mode

Front packe d

L O W

HIGH

HIGH

L O W

18 bits

HIGH

HIGH

16 bits