SM5844AF

NIPPON PRECISION CIRCUITS—18

System Clock

Input system clock (ICLK, ICKSL)

The input system clock can be set to run at either

256fsi or 384fsi, where fsi is the input frequency on

LRCI.

Note that ICLK and LRCI should be divided from a

common

clock

source

or

PLL

to

maintain

synchronism.

Output system clock (OCLK, OCKSL)

The output system clock can be set to run at either

256fso or 384fso, where fso is the input frequency on

LRCO. In through mode, OCLK and OCKSL have

no function and are not used.

Note that in slave mode, a suitable clock must be

input on OCLK. The clock on OCLK should ideally

have a protection circuit to prevent incorrect

operation for times when the clock on ICLK is

halted.

Output data interface and output clock selection (LRCO, BCKO, DOUT, SLAVE)

System Reset (RSTN)

At power-ON, all device functions must be reset. The

device is reset by applying a LOW-level pulse on

RSTN. At system reset, the internal arithmetic

operation, output timing counter and internal flag

register operation are synchronized on the next LRCI

rising edge. Note that all flags are set to their defaults

(all LOW).

A power-ON reset signal can be applied from an

external microcontroller. For systems where ICLK

and LRCI are stable at power ON, initialization can

be performed by connecting a 0.001 µF capacitor

between RSTN and VSS. Otherwise, a capacitor

value should be chosen such that RSTN does not go

HIGH until after LRCI and ICLK have stabilized.

Through Mode (THRUN)

Table 9. ICLK system clock

ICKSL

ICLK system clock rate

HIGH

384fsi

L O W

256fsi

Table 10. OCLK system clock

S L AV E

OCKSL

OCLK system clock rate

LO W

HIGH

384fso

L O W

256fso

HIGH

×

Not used

Table 11. Output mode description

T H R U N

SLAVE

Function

Mode

Description

LRCO , B C K O state

HIGH

L O W

Master mode

Output word clock (LRCO) and output bit clock

( B C KO) are divided from OCLK.

Outputs

HIGH

Slave mode

Output word clock (LRCO) and output bit clock

(BCKO) are supplied externally.

1. The number of BCKO input clock cycles should not exceed 64 per word. Correct operation is not guaranteed beyond these limits.

LO W

×

Through mode

Output word clock (LRCO), output bit clock

(BCKO) and output data (DOUT) are the

same as LRCI, BCKI and DI, respectively.

Outputs

Table 12. THRUN operation

T H R U N

Mode

Description

L O W

Through mode

Direct connections are made: LRCI

to LRCO, BCKI to BCKO , and DI to

DOUT.

HIGH

N o r mal mode

Sample rate conver ter operation