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SM5844 データシート(PDF) 19 Page - Nippon Precision Circuits Inc |
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SM5844 データシート(HTML) 19 Page - Nippon Precision Circuits Inc |
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19 / 26 page  SM5844AF NIPPON PRECISION CIRCUITS—19 Internal Arithmetic Timing Auto-reset The clock on LRCI should pass through 1 cycle for every 384 (ICKSL = HIGH) or 256 (ICKSL = LOW) ICLK clock cycles to maintain correct internal arithmetic sequence. If the number of ICLK cycles is different, increases or decreases, or any jitter is present, device operation could be affected. There is a fixed-value tolerance within which the internal sequence and LRCI clock timing are not adversely affected. Whenever the allowable tolerance is exceeded, the internal sequence is automatically reset so that the internal sequence matches the LRCI clock. When this occurs, there is a possibility that click noise will be generated. Output Format Control (OW18N, OW20N, IISN) The output is in MSB-first, 2s-complement, L/R alternating, bit serial format with a continuous bit clock. Output Timing Calculation The output timing is calculated to maintain the desired ratio between the output data cycle and the input data cycle. Filter Characteristic Selection Conversion rates from 0.5 to 2.0 times are supported using the following 4 filter types. The ratio between the output sample rate and input sample rate is measured automatically and the most suitable filter type for this ratio is selected automatically. When the selected fs conversion ratio and the actual sample rate conversion ratio do not coincide, the following phenomenon are generated. Note: An output noise may be generated if the fs conversion ratio changes at a rate greater than 0.057%/sec. Table 13. Clock tolerance ICKSL Allow a b le clock variation HIGH (384fs mode) +8/ −6 cycles L O W (256fs mode) +4/ −3 cycles Table 14. Output format selection Mode Inputs Output fo r m a t IISN O W20N O W18N Word length IIS selection Front/rear p a cking 1 HIGH HIGH HIGH 16 bits Non IIS Rear 2 HIGH L O W 18 bits 3 L O W HIGH 20 bits 4 L O W L O W 20 bits Front 5 LO W HIGH HIGH 16 bits IIS 6 HIGH L O W 18 bits 7L O W × 20 bits Table 15. fs ratio and filter selection Mode Filter fs ratio (fso/fsi) Selects range 1 Up conver ter 1.0 to 2.0 ≥ 0.97 2 48.0 to 44.1 kHz 0.91875 0.865 to 0.97 3 44.1 to 32.0 kHz 0.72562 0.711 to 0.865 4 48.0 to 32.0 kHz 0.66667 ≤ 0.711 Table 16. fs ratio mismatch Condition Affect Actual sample rate conversion ratio is low er than the selected filter conversion ratio The audio band high-pass d evelops aliasing noise. Actual sample rate conversion ratio is higher than the selected filter conversion ratio The audio band high-pass is cut off. |
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