SM5844AF

NIPPON PRECISION CIRCUITS—20

TIMING DIAGRAMS

Input Timing Examples (DI, BCKI, LRCI)

Audio data input timing (rear-packed 16-bit word, IFM1 = LOW, IFM2 = LOW)

Audio data input timing (rear-packed 20-bit word, IFM1 = LOW, IFM2 = HIGH)

Audio data input timing (front-packed 20-bit word, IFM1 = HIGH, IFM2 = LOW)

All data bits after the LSB (20th bit) are ignored. Accordingly, more than 20 BCKI cycles are required.

DI

BCKI

LRCI

Left-channel data

Right-channel data

1/fs

MSB

LSB

MSB

LSB

16

15

14

2

1

16

15

14

2

1

DI

BCKI

LRCI

Left-channel data

Right-channel data

1/fs

MSB

LSB

MSB

LSB

20

19

18

2

1

20

19

18

2

1

DI

BCKI

LRCI

Left-channel data

1/fs

MSB

LSB

1

2

3

19

20

1

2

3

19

20

Right-channel data

MSB

LSB

1