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L7292 データシート(PDF) 29 Page - STMicroelectronics |
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L7292 データシート(HTML) 29 Page - STMicroelectronics |
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29 / 60 page  DocID028601 Rev 1 29/60 L7292 Register map 60 9 Register map An internal register bank can be accessed by the I2C interface. The size of the address space is 64 (address word length = 6 bits). Not every register bit can be accessed in the read/write mode; there are also the read only and reserved bit. A read only bit can be only read and a write operation has no effect. A reserved bit returns '0' when read and a write operation has no effect. 9.1 General overview Table 16. Register map overview Address Name Description Bit Name Read/write Reset value 76 5 4 3 2 1 0 0x01 PSR1VL Power switching regulator 1 voltage level PSR1VLEN R/W 0x0 PSR1OCDI SR/W 0x0 Reserved VL[4:0] R/W Default defined by MOD pins 0x02 PSR3VL Power switching regulator 3 voltage level PSR3VLEN R/W 0x0 PSR3OCDI SR/W 0x0 Reserved VL[4:0] R/W Default defined by MOD pins 0x03 PSR2VL Power switching regulator 2 voltage level PSR2VLEN R/W 0x0 PSR2OCDI SR/W 0x0 Reserved VL[4:0] R/W Default defined by MOD pins 0x04 PSR4VL Power switching regulator 4 voltage level PSR4VLEN R/W 0x0 PSR4OCDI SR/W 0x0 Reserved L[4:0] R/W Default defined by MOD pins 0x05 PSR5VL Power switching regulator 5 voltage level PSR5VLEN R/W 0x0 PSR5OCDI SR/W 0x0 Reserved VL[4:0] R/W Default defined by MOD pins 0x07 PSR1CFG Power switching regulator 1 configuration PFMDIS R/W 0x0 ORDER[2:0] R/W 0x2 SLEW[1:0] R/W 0x3 LSDIS R/W 0x0 UVM R/W 0x0 0x08 PSR3CFG Power switching regulator 3 configuration PFMDIS R/W 0x0 ORDER[2:0] R/W 0x0 RSLEW[1:0] R/W 0x3 LSDIS R/W 0x0 UVM R/W 0x0 0x09 PSR2CFG Power switching regulator 2 configuration PFMDIS R/W 0x0 ORDER[2:0] R/W 0x3 RSLEW[1:0] R/W 0x3 LSDIS R/W 0x0 UVM R/W 0x0 0x0A PSR4CFG Power switching regulator 4 configura-tion PFMDIS R/W 0x0 ORDER[2:0] R/W 0x0 RSLEW[1:0] R/W 0x3 LSDIS R/W 0x0 UVM R/W 0x0 0x0B PSR5CFG Power switching regulator 5 configura-tion PFMDIS R/W 0x0 ORDER[2:0] R/W 0x1 RSLEW[1:0] R/W 0x3 LSDIS R/W 0x0 UVM R/W 0x0 |
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