C1

10 F

L3

2.2 H

3V

1.2V

Low = 1.0V

C6

4.7 F

L1

2.2 H

BUCK1

BUCK2

BUCK3

LDO

SPI

SW_B3

FB_B3

VIN_B3

FB_B2

SW_B2

VIN_B2

SW_B1

VIN_B1

LDO

FB_B1

CS

CLK

DO

DI

VIN

Interrupt

Vcomp

L2

2.2 H

3V

Low = 1.8V

C7

4.7 F

C5

4.7 F

C8

2.2 F

Power Supply

3.3/5.0V

Vcore

1.2V/1A

Host 3

Domain

Host 1

Flash

3.0V/1.6A

Vcc

Vccq

3.0V/1A

Host 2

Domain

LM10504

Host

Controller

Vhost

3.0V/250 mA

System

Control

C2

10 F

C3

10 F

3V

C4

4.7 F

COMP

Reset

VIN_IO

C9

2.2 F

IO input

supply

DevSLP

Voltage Monitored

@ Startup

LM10504

SNVS739E – DECEMBER 2011 – REVISED MARCH 2013

www.ti.com

Typical Application Diagram

Overview

The LM10504 contains three buck converters and one LDO. Table 1 below lists the output characteristics of the

power regulators.

SUPPLY SPECIFICATION

Table 1. Output Voltage Configurations for LM10504

Vselect=Hi

Vselect=L

Maximum

Typical

Regulator

DEVSLP=High

Comments

gh

ow

Output Current

Application

(DevSLP Mode)

(B2, B3)

(B2, B3)

1.1V to 3.6V;

3.0V

3.0V

off

1.6A

Flash

50 mV steps

1.1V to 3.6V;

3.0V

1.8V

off

1A

Interface

50 mV steps

0.7V to 1.335V;

1.2V

1.0V

Vnomimal

−7%

1A

Core

5mV steps

Reference for

LDO

3.0V

3.0V

3.0V

3.0V

250 mA

controller

Host

(1)

Default voltage values are determined when working in PWM mode. Voltage may be 0.8-1.6% higher when in PFM mode.

2

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