TMS570LS0332PZ datasheet(49/110 Pages) TI1

49 / 110 page

TMS570LS0432, TMS570LS0332

www.ti.com

SPNS186B – OCTOBER 2012 – REVISED JUNE 2015

6.8.3

Master/Slave Access Privileges

The table below lists the access permissions for each bus master on the device. A bus master is a module

that can initiate a read or a write transaction on the device.

Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed

in the "MASTERS" column can access that slave module.

Table 6-18. Master / Slave Access Matrix

SLAVES ON MAIN SCR

Peripheral Control

Registers, All

Flash Module Bus2

Non-CPU Accesses

Peripheral

MASTERS

ACCESS MODE

Interface:

to Program Flash

CRC

Memories, And All

OTP, ECC, EEPROM

and CPU Data RAM

System Module

Bank

Control Registers

And Memories

CPU READ

User/Privilege

Yes

CPU WRITE

User/Privilege

Yes

HTU

Privilege

Yes

System Information and Electrical Specifications

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