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TMS570LS0332PZ データシート(PDF) 57 Page - Texas Instruments |
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TMS570LS0332PZ データシート(HTML) 57 Page - Texas Instruments |
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57 / 110 page ![]() TMS570LS0432, TMS570LS0332 www.ti.com SPNS186B – OCTOBER 2012 – REVISED JUNE 2015 Table 6-24. Interrupt Request Assignments (continued) DEFAULT VIM MODULES INTERRUPT SOURCES INTERRUPT CHANNEL MIBSPI1 MIBSPI1 level 1 interrupt 26 LIN LIN level 1 interrupt 27 MIBADC MIBADC sw group 2 interrupt 28 DCAN1 DCAN1 level 1 interrupt 29 SPI2 SPI2 level 1 interrupt 30 MIBADC MIBADC magnitude compare interrupt 31 Reserved Reserved 32-34 DCAN2 DCAN2 level 0 interrupt 35 Reserved Reserved 36 SPI3 SPI3 level 0 interrupt 37 SPI3 SPI3 level 1 interrupt 38 Reserved Reserved 39-41 DCAN2 DCAN2 level 1 interrupt 42 Reserved Reserved 43-60 FMC FSM_DONE interrupt 61 Reserved Reserved 62-79 HWAG HWA_INT_REQ_H 80 Reserved Reserved 81 DCC DCC done interrupt 82 Reserved Reserved 83 eQEPINTn eQEP Interrupt 84 PBIST PBIST Done Interrupt 85 Reserved Reserved 86-87 HWAG HWA_INT_REQ_L 88 Reserved Reserved 89-95 NOTE Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR entry; therefore only request channels 0..94 can be used and are offset by 1 address in the VIM RAM. Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications 57 Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332 |
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