DM6381F datasheet(29/40 Pages) ETC

29 / 40 page

DM336P

V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set

Final

Version: DM336P-DS-F02

August 15, 2000

• Chip 3 : DM6380 Analog Front End (AFE) Description

DM6380 Description

The DM6380 is a single chip Analog Front End (AFE)

designed to implement voice grade modem up to

33600bps. It is used as a portion of a complete

modem device set. The AFE converts the analog

signal into digital form and transfers the digital data to

the DSP through the serial port. All the clock

information needed in a modem device is also

generated in this device. The differential analog

outputs are provided to acquire the maximum output

signal level. An audio monitor whose volume is

programmable is built in to monitor the on-line signal.

Inside the device, a 16-bit ADC and a 16-bit DAC with

over-sampling and noise-shaping techniques is

implemented to maximize performance for high speed

modem. It offers wide-band transmit and receive

filters so that the voice band signal is transmitted or

received without amplitude distortion and with

minimum group delay. In order to support the multi-

mode modem standards, such as V.34, V.32bis, V.32,

V.22bis, V.22, V.23, V.21, Bell 212A, Bell 103, V.17,

V.29, V.27ter, the programmable baud and data rate

clock generators are provided. For the asymmetric

channel usage, the transmit and receive clock

generators are independent. In order to provide the

echo-cancel capability, the receive clock is

synchronized with the transmit clock and the best

receive timing sample is reconstructed by a

reconstruction filter. Transmit Digital Phase Lock

Loop (DPLL) is self-tuning to provide the master,

slave or free-running mode for the data terminal

interface. A software programmable receive DPLL

that is step-controllable by the host DSP is

implemented to get the best samples for the relevant

signal processing.

DM6380 Block Diagram

RxSCLK

RxDCLK

RFS

DOR

DIR

TFS

DOT

DIT

Digital

Reconstruction

Filter

SCLK

Digital

Interface

Rx Clock

System

Tx Clock

System

Divider

Control

Registers

Tx Filter &

DAC

Rx Filter &

ADC

LPF &

Attenuator

Voltage Reference

0/-6 dB

Audio Amplifier

Power-on

Detector

SPKR

RxIN

V REFN

V REFP

TxA2

TxA1

CLKIN

TxSCLK*2

TxDCLK

ExtCLK

V CM

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