DM6381F datasheet(31/40 Pages) ETC

31 / 40 page

DM336P

V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set

Final

Version: DM336P-DS-F02

August 15, 2000

DM6380 Pin Description

Pin No.

Pin Name

I/O

Description

RXDCLK

Receive Data Clock

VDD

Digital Power

RXSCLK

Receive Sample Clock

RFS

Receive Frame Synchronization

DOR

Data Output For Receiver

DIR

Data Input For Receiver

DGND

Digital Ground

SCLK

Serial Clock Synchronized With All Serial Data

DOT

Data Output For Transmitter

DIT

Data Input For Transmitter

TFS

Transmit Frame Synchronization

TXSCLK*2

Transmit Sample Clock * 2

TXDCLK

Transmit Data Clock

CLKIN

Master Clock Input (20.16MHz = 40.32MHz / 2 )

/RESET

Codec Reset Input

EXTCLK

External Transmit Data Clock

Internal Reference Voltage. Connect 0.1uF to DGND

AVDDT

Analog VDD For The Transmitter Analog Circuitry (+5VDC)

TXA2

Transmit Negative Analog Output

TXA1

Transmit Positive Analog Output

AGNDR

Analog Receiver Circuitry Signal Return Path

VREFN

Negative Reference Voltage, VCM - 1V

VCM

Common Mode Voltage Output, 2.5V

VREFP

Positive Reference Voltage, VCM + 1V

AGNDT

Analog Transmitter Circuitry Signal Return Path

RXIN

Receive Analog Input

AVDDR

Analog VDD For The Receiver Analog Circuitry (+5VDC)

SPKR

Speaker Driver

DM6380 Functional Description

In this chip, we could roughly divide it into two major

parts : digital portion and analog portion. The

functional blocks are described separately in this

section. The analog circuits include a sigma-delta

modulator/demodulator, decimation/interpolation

filters, a speaker driver, low-pass filter and certain

logic circuits. The digital circuits is composed of Tx/Rx

clock generator/PLL, serial port, serial/parallel

conversions and control registers. All the clock

information the analog circuits need should be

provided by the digital clock system since the best

sampling instant of A/D and D/A depends on the

received signal and transmit signals. The data format

of A/D and D/A is 2's complement.

Master clock (FQ) is obtained from an external signal

connected to CLKIN. The different transmit and

receive clocks are obtained by master clock

frequency division in several programmable counters.

The Tx and Rx clocks can be synchronized on

external signals by performing the phase shifts in the

frequency division process. Two independent digital

phase locked loops are implemented using this

principle, one for transmit clock system, the other,

receive clock. The tracking of the transmit clock is

automatically done by the transmit DPLL circuit. The

receive DPLL circuit is controlled by the host

processor and it is actually an adjustable phase

shifter.

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