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ST7MC1 データシート(PDF) 277 Page - STMicroelectronics |
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ST7MC1 データシート(HTML) 277 Page - STMicroelectronics |
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277 / 308 page ![]() ST7MC1/ST7MC2 277/308 MOTOR CONTROL CHARACTERISTICS (Cont’d) 12.12.3 Input Stage (Current Feedback Comparator + Sampling) Notes: 1. The comparator accuracy depends on the environment. In particular, the following cases may reduce the accuracy of the comparator and must be avoided: – Negative injection current on the I/Os close to the comparator inputs – Switching on I/Os close to the comparator inputs – Negative injection current on not used comparator input (MCCFI0 or MCCFI1) – Switching with a high dV/dt on not used comparator input (MCCFI0 or MCCFI1) These phenomena are even more critical when a big external serial resistor is added on the inputs. 2. This filter is implemented to wait for comparator stabilization and avoid any wrong information during start-up. 3.This delay represents the number of clock cycles needed to generate an event as soon as the comparator ouput chang- es. Example: When CFF=0 (detection is based on a single detection), MCO outputs are turned OFF at the 4th clock cycle after comparator commutation, i.e. there is a variation of (1/fmtc) or (4 / fPERIPH) depending on the case. Symbol Parameter Conditions Min Typ Max Unit VIN Comparator input voltage range VSSA - 0.1 VDD + 0.1 V Voffset Comparator offset error 5 40 1) mV Ioffset Input offset current 1 µA tpropag Comparator propagation delay 1) 35 100 ns tstartup Start-up filter duration 2) Time waited before sampling when comparator is turned ON, i.e. CKE=1 or DAC=1 (with fPERIPH = 4MHz) 3 µs tsampling Digital sampling delay 3) Time needed to turn OFF the MCOs when comparator out- put rises (CFF=0) 4 / f MTC (see Figure 155) Time between a comparator toggle (current loop event) and bit CL becoming set (CFF=0) 2 / f MTC (see Figure 155) Time needed to turn OFF the MCOs when comparator out- put rises (CFF=x) (1+x) * (4 / fPERIPH) + (3 / fmtc) (see Figure 156) Time between a comparator toggle (current loop event) and bit CL becoming set (CFF=x) (1+x) * (4 / fPERIPH) + (1 / fmtc) (see Figure 156) |
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