データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

VDP313XY データシート(PDF) 34 Page - Micronas

部品番号 VDP313XY
部品情報  Video Processor Family
PDF  76 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  MICRONAS [Micronas]
ホームページ  http://www.micronas.com
Logo MICRONAS - Micronas

VDP313XY データシート(HTML) 34 Page - Micronas

Back Button VDP313XY Datasheet HTML 30Page - Micronas VDP313XY Datasheet HTML 31Page - Micronas VDP313XY Datasheet HTML 32Page - Micronas VDP313XY Datasheet HTML 33Page - Micronas VDP313XY Datasheet HTML 34Page - Micronas VDP313XY Datasheet HTML 35Page - Micronas VDP313XY Datasheet HTML 36Page - Micronas VDP313XY Datasheet HTML 37Page - Micronas VDP313XY Datasheet HTML 38Page - Micronas Next Button
Zoom Inzoom in Zoom Outzoom out
 34 / 76 page
background image
VDP 313xY
ADVANCE INFORMATION
34
Micronas
Picture Frame Generator
47
9
w v
bit[7:0]
reserved, set t o zero
bit[8]
1
enable picture frame generator
0
PFGEN
11
16
w h
picture frame color 12 bit wide,
bit[3:0]
0..15
blue amplitude
bit[7:4]
0..15
green amplitude
bit[11:8]
0..15
red amplitude
0
0
0
PFC
PFCB
PFCG
PFCR
4C
9
w v
picture frame insertion contrast for R
(ampl. range: 0 to 255)
bit[3:0]
reserved, set to zero
bit[7:4]
0..13
R amplitude =
PFCR
× (PFRCT + 4)
14,15
invalid
8
PFRCT
48
9
w v
picture frame insertion contrast for G
(ampl. range: 0 to 255)
bit[3:0]
reserved, set to zero
bit[7:4]
0..13
G amplitude =
PFCG
× (PFGCT + 4)
14,15
invalid
8
PFGCT
44
9
w v
picture frame insertion contrast for B
(ampl. range: 0 to 255)
bit[3:0]
reserved, set to zero
bit[7:4]
0..13
B amplitude =
PFCB
× (PFBCT + 4)
14,15
invalid
8
PFBCT
4F
9
w v
bit[8:0]
horizontal picture frame begin
code 0 = picture frame generator horizontally disabled
code 1FF = full frame
0PFGHB
53
9
w v
bit[8:0]
horizontal picture frame end
0
PFGHE
63
9
w v
bit[8:0]
vertical picture frame begin
code 0 = picture frame generator vertically disabled
270
PFGVB
6F
9
w v
bit[8:0]
vertical picture frame end
56
PFGVE
Priority Decoder
75
9
w v
bit[7]
0/1
select main/side setting for
contrast,brightness,matrix
0SIDE
79
9
w v
bit[7]
0/1
disable/enable peaking transient
suppression when signal is
switched to the picture frame
0
PKTRNS
Table 2–5: I2C control and status registers of the video backend
(Registers are set to ’0’ at reset, default values are recommendations)
I2C Sub
address
Number
of bits
Mode
Function
Default
Name
(hex)
(hex)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com