データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

VDP313XY データシート(PDF) 38 Page - Micronas

部品番号 VDP313XY
部品情報  Video Processor Family
PDF  76 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  MICRONAS [Micronas]
ホームページ  http://www.micronas.com
Logo MICRONAS - Micronas

VDP313XY データシート(HTML) 38 Page - Micronas

Back Button VDP313XY Datasheet HTML 34Page - Micronas VDP313XY Datasheet HTML 35Page - Micronas VDP313XY Datasheet HTML 36Page - Micronas VDP313XY Datasheet HTML 37Page - Micronas VDP313XY Datasheet HTML 38Page - Micronas VDP313XY Datasheet HTML 39Page - Micronas VDP313XY Datasheet HTML 40Page - Micronas VDP313XY Datasheet HTML 41Page - Micronas VDP313XY Datasheet HTML 42Page - Micronas Next Button
Zoom Inzoom in Zoom Outzoom out
 38 / 76 page
background image
VDP 313xY
ADVANCE INFORMATION
38
Micronas
62
66
6A
9
9
9
w v
w v
w v
PLL2/3 filter coefficients, 1of5 bit code
(n+ set bit number)
bit[5:0]
proportional coefficient PLL3, 2−n−1
bit[5:0]
proportional coefficient PLL2, 2−n−1
bit[5:0]
integral coefficient PLL2, 2−n−5
2
1
2
PKP3
PKP2
PKI2
15
16
w/r
horizontal drive and vertical signal control register
bit[5:0]
0..63
horizontal drive pulse duration in
µs (internally limited to 4..61)
bit[6]
0/1
disable/enable horizontal PLL2
and PLL3
bit[7]
0/1
1: disable horizontal drive pulse
during flyback
bit[8]
0/1
reserved, set to ’0’
bit[9]
0/1
enable/disable ultra black
blanking
bit[10]
0/1
0: all outputs blanked
1: normal mode
bit[11]
0/1
enable/disable clamping for
analog RGB input
bit[12]
0/1
disable/enable vertical free
running mode (FIELD is set to
field2, no interlace)
bit[13]
0/1
enable/disable vertical protection
bit[14]
reserved (set to 0)
bit[15]
0/1
disable/enable phase shift of
display clock
32
0
0
0
0
1
0
0
0
0
1
HVC
HDRV
EHPLL
EFLB
DUBL
EBL
DCRGB
SELFT
DVPR
DISKA
9D
8
w/r
sync output control
bit[0]
invert INTLC
bit[1]
disable INTLC (tristateINTLC output)
bit[2]
invert VS
bit[3]
disable VS
bit[4]
disable CSY
bit[5]
force INTLC to polarity defined in
’INTLCINV’
0
SYCTRL
9E
8
w/r
delay of CSY output (relative to PLL2)
bit[7:0]
−128..127 ± 8 µs
0
CSYDEL
Table 2–5: I2C control and status registers of the video backend
(Registers are set to ’0’ at reset, default values are recommendations)
I2C Sub
address
Number
of bits
Mode
Function
Default
Name
(hex)
(hex)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com