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VDP313XY データシート(PDF) 39 Page - Micronas

部品番号 VDP313XY
部品情報  Video Processor Family
PDF  76 Pages
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メーカー  MICRONAS [Micronas]
ホームページ  http://www.micronas.com
Logo MICRONAS - Micronas

VDP313XY データシート(HTML) 39 Page - Micronas

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ADVANCE INFORMATION
VDP 313xY
Micronas
39
Analog RGB Insertion
4B
9
w v
bit[7]
0/1
disable/enable analog fast blank
input for RGB inserion
0ERGB
4B
9
w v
bit[0]
0
Picture frame overOSD
1
OSD over picture frame
0
OSDPRIO
32
8
w/r
fast blank interface mode
bit[0]
0
internal fast blank 1 from FBLIN1
pin
1
force internal fast blank 1 signal
to high
bit[1]
0/1
internal fast blank active high/low
bit[2]
0/1
disable/enable clamping
reference for RGB outputs
bit[3]
1
full line MADC measurement
window, disables bit [3] in
address 25
bit[4]
0/1
horizontal flyback input active
high/low
bit[6:5]
reserved (set to 0)
bit[7]
0
internal fast blank 1 from FBLIN1
pin
1
force internal fast blank 1 signal
to low
0FBMOD
FBFOH1
FBPOL
CLMPR
FLMW
FLPOL
FBFOL1
31
8
w/r
fast blank interface mode 2
bit[0]
0
internal fast blank 2 from FBLIN2
pin
1
force internal fast blank 2 signal
to high
bit[1]
0
internal fast blank 2 from FBLIN2
pin
1
force internal fast blank 2signal to
low
bit[2]
fast blank input priority
0
FBLIN1>FBLIN2
1
FBLIN2>FBLIN1
bit[3]
fast blank monitor input select
0
monitor connected to FBLIN1 pin
1
monitor connected to FBLIN2 pin
bit[4]
half contrast switch enable
0/1
HCS disable/enable
bit[5]
0
half contrast from HCS pin
1
force half contrast signal to high
bit[6]
0/1
half contrast active high/low at
HCS pin
bit[7]
reserved (set to 0)
0FBMOD2
FBFOH2
FBFOL2
FBPRIO
FBMON
HCSEN
HCSFOH
HCSPOL
Table 2–5: I2C control and status registers of the video backend
(Registers are set to ’0’ at reset, default values are recommendations)
I2C Sub
address
Number
of bits
Mode
Function
Default
Name
(hex)
(hex)



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