VDP313XY datasheet(28/76 Pages) MICRONAS

28 / 76 page

VDP 313xY

ADVANCE INFORMATION

Micronas

2.12.5.EHT Compensation

The vertical waveform can be scaled according the

average beam current. This is used to compensate the

effects of electric high tension changes due to beam

current variations. EHT compensation for East/West

deflection is done with an offset corresponding to the

average beam current.

2.12.6.Protection Circuitry

– Picture tube and drive stage protection is provided

through the following measures:

– Vertical flyback protection input: this pin searches

for a negative edge in every field, otherwise the

RGB drive signals are blanked.

– Drive shutoff during flyback: this feature can be

selected by software.

– Safety input pin: this input has two thresholds.

Between zero and the lower threshold, normal func-

tioning takes place. Between the lower and the

higher threshold, the RGB signals are blanked.

Above the higher threshold, the RGB signals are

blanked and the horizontal drive is shut off. Both

thresholds have a small hysteresis.

– The main oscillator and the horizontal drive circuitry

are run from a separate (standby) power supply and

are already active while the TV set is powering up.

2.13.Reset and Power On

Reset of most VDP 313xY functions is performed by

the RESQ pin. When this pin becomes active all inter-

nal registers and counters are lost. When the RESQ

pin is released, the internal reset is still active for 4

µs.

After that time, the initialization of all required registers

is performed by the internal Fast Processor.

The VDP 313xY has clock and voltage supervision cir-

cuits to generate a stable HOUT signal. The voltage

supervision activates an internal reset signal when the

supply for the digital circuits (VSUPD) goes below

~2.5 V for more than 50 ns. This reset signal is

extended by 50

µs after VSUP

D is back again.

After power on or reset the HOUT generation is

switched to a freerunning mode with a fix duty cycle of

50 %. For normal operation the EHPLL bit has to be

set first. During the switch the actual period of HOUT

can vary by up to 1

µs.

Fig. 2–26: External Reset

µs

approx. 60

µs

Reset

Initialization

Internal

Reset

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