ADP3500

REV.PrP 2/6/02

- 20 -

Figure 11. Serial I/F Data read/write timing

SP_ADDR[5:0]

: 6bit address

SP_CTRL[1:0]

: 2bit Read/Write control (01: Write, 10: Read)

SP_DATA[7:0]

: 8bit Input/Output Data

* All transfer will be done MSB first.

2.3 GPIO+INT

GPIO block has 4 channel I/O function and interrupt. With GPIO CONTROL register (1Ah), it is possible to control Input or

Output setting of each channel individually. The output data is set in GPIO register (1Ch). When the port is set as input mode,

the input signal transition from “1” to “0” and from “0” to “1”, then generate interrupt signal with Edge detection. The held

interrupt signals are reset by GPIO INT RESET register (1Dh). Setting GPIO MASK register (1Bh) to “1” enables the

interrupt of GPIO. (Not MASKED, “1” at default in reset.)

2.4 INT REGISTER

In case the interrupt event has occurred, “1”, the signal is held in this register. INT detect and Reset are synchronized at the

rising edge of CLK32K. In case the interrupt event and reset signal are occurred at same time, interrupt event has priority.

RESETIN_N signal resets INT register (1Eh) to “0” (No INT detected), except alarm_int and ctfg_int. INT MASK register

(1Fh) to “1” (not masked). This block masks alarm_int and ctfg_int, which generated in RTCV block, but these signals are

reset with ALARM CONTROL register (0Dh) and CTFG CONTROL register (0Eh). The interrupt signal, INT_N, is an

“inverted OR” signal of value in INT register and GPIO register.

DATA-IN register is a port to read an interrupt status. The input data are through SYNC block except Alarm signal. Since this

is for just read back purpose, user cannot write any data.

BATID

RTC Alarm

Charger_Detect

OPT3

OPT1-

PWRONKEY-

SYNC block

DATA_IN registor (Addr: 20h)

Register

Figure 12. DATA-IN block

2.5 KEYPAD CONTROL & LED DRIVE

KEYPADCOL[3:0] are Open Drain output. The KEYPADROW[5:0] are Falling edge trigger input (input state transition from

“1” to “0”) and generate Interrupt signal, and are pulled up to LDO1. By providing 4 keypad-column outputs and 6 keypad-

row inputs the ADP3500 can monitor up to 24 keys with baseband chip. Writing Column outputs and Reading Row inputs are

controlled through serial interface. The address of the KEYPADROW is 19h, and KEYPADCOL is 18h. Initial register value

is “0” that means an output of KEYPADCOL is “High Impedance”.

Back-light drive is an open drain output. Maximum current of internal FET is 100mA. Initial register value is “0” that means

the output of BLIGHT is “High impedance”.

PRELIMINARY TECHNICAL DATA