ADP3500

REV.PrP 2/6/02

- 24 -

USEC

Counter

RTC

Counter

Loading Alarm times

RTC_WRITE_ENABLE

RTC_CLK32K

rtc_data[7:0]

rtc_alarm_int

RTC_CS

rtc_ctfg_int

RTC_WRITE_DATA[7:0]

(from serial I/F)

RTC

Register

block

RTC_SP_ADDR[5:0]

Alarm

Comparator

Periodic

Interrupt

Data

Select

leap year

and Date

Control

Reset will be asserted when

RTC counter is writed.

Registers for

Test mode

- Reset to RTC & USEC counters

- Write initial data of USEC counter

Sec counter

Increment

control

Figure 15. RTC counter block

2.9.2 Operation

Synchronizing with RTC_CLK32K clock, USEC counter generates 1sec timing clock and the clock hits RTC counter.

Through the serial interface, CPU can write setting value and read RTC counter value. In case the RTC counter toggles during

the serial interface access to RTC counter, the wrong data can be read/write between RTC counter and interface. CS signal

stops the clocking to RTC counter until CS signal is released. In case CPU writes data into SEC counter, USEC counter is

reset to zero.

Note

•

In case of RTC counter access, the access should be waited approximately 62

µS, (2 clock cycles of CLK32K) after the

CS signal is asserted, to hold the RTC value.

•

CS signal should never be asserted 1sec or longer, this affects counter operation.

2.9.3 Operation of USEC counter

USEC counter counts up synchronizing with RTC_CLK32K clock. It generates 1sec timing signal and it is used as an

increment clocking of RTC counter. In case the 1sec signal is generated during CS signal asserted, the increment clock is

delayed until CS signal is released.

2.9.4 Operation of RTC counter

RTC counter uses the increment signal from USEC counter to control counting operation including the leap year control and

numbers of days in a month control.

PRELIMINARY TECHNICAL DATA