ST95HF datasheet(55/93 Pages) STMICROELECTRONICS

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ST95HF

Electrical characteristics

6.4

SPI characteristics

The ST95HF supports (CPOL = 0, CPHA = 0) and (CPOL = 1, CPHA = 1) modes.

Figure 12. SPI timing diagram (Slave mode and CPOL = 0, CPHA = 0)

Table 49. SPI interface characteristics

Symbol

Parameter

Condition

Min.

Max.

Unit

fSCK

1/ tc(SCK)

SPI clock frequency

2.0

MHz

VIL

Input low voltage

0.3 x VPS

VIH

Input high voltage

0.7 x VPS

VOL

Output low voltage

0.4 x VPS

VOH

Output high voltage

0.7 x VPS

tSU(NSS)(1)

1. Values based on design simulation and/or characterization results, and not on tested in production.

NSS setup time

th(NSS)(1)

NSS hold time

tCH(SCKL)(1) Clock low time

200

tCH(SCKH)(1) Clock high time

200

tSU(SI)(1)

Data slave Input setup time

th(SI)(1)

Data slave Input hold time

tv(SO)(1)

Data slave output valid time

th(SO)(1)

Data slave output hold time

After enable edge

Cb_SPI_IN

Capacitive load for input pins NSS,

CLK, MOSI

Cb_SPI_OUT Capacitive load for input pins MOSI

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