STS1TX datasheet(58/70 Pages) STMICROELECTRONICS

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STS1TX

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DocID025109 Rev 1

SYNTH_CONFIG[0]

0x9F

SEL_TSPLIT

R/W

0: split time: 1.75 ns

1: split time: 3.47 ns

6:0

Reserved

0100000

SYNTH_CONFIG[1]

0x9E

7REFDIV

R/W

Enable division by 2 on the

reference clock:

0: fREF = fXO frequency

1: fREF = fXO frequency / 2

6:3

Reserved

1011

VCO_L_SEL

1: enable VCO_L

VCO_H_SEL

1: enable VCO_H

0Reserved

Table 34. General configuration registers (continued)

Address

Bit

Field name

Reset

R/W

Description

Table 35. Radio configuration registers (analog blocks)

Address

Bit

Field Name

Reset

R/W

Description

SYNT3

0x08

7:5

WCP[2:0]

000

R/W

Set the charge pump current

according to the VCO

frequency. See Table 24.

4:0

SYNT[25:21]

01100

SYNT[25:21], highest 5 bits of

the PLL programmable divider

The valid range depends on

fXO and REFDIV settings; for

fXO=26MHz. See Equation 2

SYNT2

0x09

7:0

SYNT[20:13]

0x84

R/W

SYNT[20:13], intermediate bits

of the PLL programmable

divider. See Equation 2

SYNT1

0x0A

7:0

SYNT[12:5]

0xEC

R/W

SYNT[12:5], intermediate bits

of the PLL programmable

divider. See Equation 2

SYNT0

0x0B

7:3

SYNT[4:0]

01010

R/W

SYNT[4:0], lowest bits of the

PLL programmable divider.

See Equation 2

2:0

001

R/W

Synthesizer band select. This

parameter selects the out-of-

loop divide factor of the

synthesizer (B in Equation 2).

1: 6 Band select factor for high

band

3: 12 Band select factor for

middle band

4: 16 Band select factor for low

band

5: 32 Band select factor for

very low band

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