STGAP1STR datasheet(59/67 Pages) STMICROELECTRONICS

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STGAP1S

Programming manual

9.2.7

STATUS2 register (low voltage side)

The STATUS2 is a read only register. The STATUS2 register has the structure of Table 49.

A description of the STATUS2 register bits is provided in Table 50.

9.2.8

STATUS3 register (low voltage side)

The STATUS3 is a read only register. The STATUS3 register has the structure of Table 51.

Table 49. STATUS2 register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

REGERRR

ASC

GATE

Default(1)

Reset

1. Default value of the local copy of the register. The value will be updated according to the actual information from the

isolated side. The default is forced at the device power-up, when the registers are reset all the flags are forced low (no

failures).

Table 50. STATUS2 register description

Name

Bit

Fault

Latched

Force

“safe state”

Note

REGERRR

It is forced high when:

– Programming procedure is not correctly

performed.

– Isolated interface communication fails.

– An unexpected register value change occurs in

one of the remote registers.

It is also latched at power-up/reset and from Sleep

state.

Always

Yes

This flag is

released when

a programming

procedure is

correctly

performed also.

ASC

ASC pin status.

When ASC pin is high the flag reports '1', otherwise

is '0'.

See details in

Section 7.12 on

page 36

GATE

Gate status flag.

When GON is active the flag is '1', when GOFF is

active it is '0'.

Table 51. STATUS3 register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DT_ERR

SPI_ERR

REGERRL

OVLOD

UVLOD

Default(1)

Reset

1. The default is forced at the device power-up, when the registers are reset all the flags are forced low (no failures).

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