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TNETV1647GSTZWT データシート(PDF) 85 Page - Texas Instruments

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部品番号 TNETV1647GSTZWT
部品情報  Digital Media System-on-Chip
PDF  236 Pages
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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TNETV1647GSTZWT データシート(HTML) 85 Page - Texas Instruments

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TMS320DM6441
www.ti.com
SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010
3.5.6.10 HPI and EMIFA/ATA Pin Multiplexing
When the HPIEN bit is set, the HPI module is given control of most of the EMIFA/ATA control pins as well
as the EMIFA/ATA data bus. Table 3-33 shows which pins the HPI controls. HPIEN is set to 1 when the
state of the BTSEL[1:0] pins = 10 is latched at the rising edge of reset. Also, this bit can be manipulated
after reset by software. When the ATAEN bit is set and HPIEN is 0, the ATA mode of operation for pins
shared with the HPI is available. EMIFA mode functionality for the shared HPI pins is set when both
HPIEN and ATAEN are '0'.
Table 3-33. HPI and EMIFA/ATA Pin Multiplexing
PINMUX0
REGISTER
MULTIPLEXED PINS
BIT FIELDS
HR/W/
HRDY/
HDS1/
HDS2/
HCNTLB/
HINT/
HD[15:0]/
HPI
ATA
HCS/
HHWIL/
HCNTLA/
INTRQ/
EM_WAIT/
DIOR/
DIOW/
ATA2/
ATA0/
DD[15:0]/
EN
EN
EM_CS2
EM_A[1]
EM_A[2]
EM_R/W
IORDY
EM_OE
EM_WE
EM_A[0]
EM_BA[0]
EM_D[15:0]
0
0
EM_CS2
EM_A[1](1)
EM_R/W
EM_WAIT
EM_OE
EM_WE
EM_A[2](1)
EM_A[0](1)
EM_BA[0]
EM_D[15:0]
0
1
EM_CS2
EM_A[1](1)
INTRQ
IORDY
DIOR
DIOW
EM_A[2](1)
EM_A[0](1)
ATA0
DD[15:0]
1
-
HCS
HHWIL
HR/W
HRDY
HDS1
HDS2
HCNTLA
HCNTLB
HINT
HD[15:0]
(1)
This pin shares GPIO functionality and is set by AEAW[4:0] as shown in Table 3-12, Table 3-13, and Table 3-14.
Copyright © 2006–2010, Texas Instruments Incorporated
Device Configurations
85
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